8086 Interrupts

sources of Interrupt in 8086

An interrupt in 8086 can be come in folowing ways:

1. From an external signal applied to NMI or INTR input pin of the processor. The interrupts initiated by applying appropriate signals to these input pins are called hardware interrupt.
2. The second source of interrupt is execution of the interrupt instruction “INT n”, where n is the type number. The interrupt initiated by “INT n” instruction are called software interrupts.
3. The third source of interrupt is  from some conditions produced in the 8086 by the execution of an instruction. An example of this type of interrupt ‘devided by zero interrupt’. Program execution will be automatically interrupted if you attempted to divide an operand by zero. Such conditional interrups are known as exceptions.

Interrupts of 8086

The 8086 microprocessor has 256 types of interrupts which come from any one of the three sources mentioned above. INTEL has assigned a type number to each interrupt. The type numbers are in the range of 0 to 255₁₀. The 8086 processor has dual facility of initiating these 256 interrupts. The interrupts can be initiated either by executing “INT n” instruction where n is the type number or the interrupt can be initiated by sending an appropriate signal to INTR input pin of the processor.

For the interrupts initiated by software instruction “INT n”, the type number is specified by the instruction itself. When the interrupt is initiated through INTR pin, then the processor runs an interrupt acknowledge cycle to get the type number (i.e., the interrupting device should supply the type number through D₀-D₇lines when the processor requests for the same through an interrupt acknowledge cycle).

In these 256 interrupts, INTEL has defined the functions of the first five interrupts, i.e., the interrupts type-0 to type-4 are dedicated for specific functions by INTEL and they are called INTEL predefined interrupts. The next 27 interrupts, i.e., from type-5 to type-31 are reserved by INTEL for use in future microprocessors or for system calls/services. The upper 224 interrupts, i.e., from type-32 to type-255 are available for the user as hardware or software interrupts.

Intel Predefined or Dedicated Interrupts

The INTEL predefined interrupts for 8086 are;

1. Division by zero(Type-0) interrupt.
2. Single step(Type-1) interrupt.
3. Nonmaskable interrupt, NMI(Type-2) interrupt.
4. Breakpoint(Type-3) interrupt.
5. Interrupt on overflow(Type-4) interrupt.

The predefined intenupts are only defined by INTEL and INTEL has not provided any subroutine or procedure to be executed for these interrupts. To use the predefined interrupts the user/system designer has to write Interrupt Service Subroutine (ISS) for each interrupt and store them in memory. The corresponding address of the ISS should be stored in interrupt vector table. If a predefined interrupt is not used in a system then the user may assign some other functions to these Interrupts.

Devide by zero(type-0) Interrupt

Type-0 interrupt is implemented by INTEL as a part of the execution of the divide instruction. The 8086 will automatically do a type-0 interrupt if the result of a division operation is too large to fit in the destination register and this interrupt is nonmaskable. Since the type-0 interrupt cannot be disabled in any way, we have to account for it in the programs using divide instructions. To account for this, we have to write an ISS which takes the desired action or indicate error condition when an invalid division occurs. The ISS should be stored in memory and the address of ISS is stored in interrupt vector table.

Single Step(type-1) Interrupt

When the Trap/Trace Flag (TF) is set to one, the 8086 processor will automatically generate a type-1 interrupt after execution of each instruction. The user can write an ISS for type-1 interrupt to halt the processor temporarily and return the control to the user so that after execution of each instruction, the processor status (content of register/memory) can be verified. If they are correct then we can proceed to execute the next instruction. Execution of one instruction by one instruction is known as single step and this feature will be useful to debug a program.

Non-Maskable(type-2) Interrupt

The 8086 processor will automatically generate a type-2 interrupt when it receives a low-to-high transition on its NMI input pin. This interrupt cannot be disabled or masked. Usually, the type-2 interrupt is used to save program data or processor status in case of system ac power failure.

The ac power failure is detected by an external hardware and whenever the ac power fails, the external hardware will send an interrupt signal to the NMI input pin of the processor. The rectifier which converts ac to dc usually has a large filter capacitor and so it can retain the dc power for atleast 50 milli second, after the ac power supply is interrupted. This 50 milli second time will be sufficient to run an ISS by type-2 interrupt to save program data or processor status to NVRAM or RAM with battery back-up power supply.

Breakpoint(type-3) Interrupt

Type-3 interrupt is used to implement a breakpoint function, which executes a program partly or up to the desired point and then return the control to the user.

The breakpoint interrupt is initiated by the execution of “INT 3” instructions. To implement the breakpoint function the system designer has to write an ISS for type-3, which takes care of displaying a message and return the control to the user whenever type-3 interrupt is initiated.

This interrupt will be useful to debug a program by executing the program part by part. The user can insert “INT 3” instruction at the desired location and execute the program. Whenever “INT 3” instruction is encountered, the processor halts the program execution and return the control to the user. Now the user can verify the processor status (contents of register/memory). If they are correct then the user can proceed to execute next part of the program.

Overflow (type-4) Interrupt

In the 8086 processor, the Overflow Flag (OF) will be set if the signed arithmetic operation generates such a result whose size is larger than the size of the destination register/memory. During conditions, the type-4 interrupt can be used to indicate an error condition. The type-4 interrupt is initiated by “INTO” instruction.

One way of detecting the overflow error is to put the “INTO” instruction immediately after the arithmetic instruction in the program. After arithmetic operation if the overflow flag is not set then the processor will consider “INTO” instruction as NOP (No operation). However, if the overflow flag is set then the 8086 will generate a type-4 interrrupt, which executes an-ISS to indicate overflow condition.

Organisation of Interrupt Vector Table(IVT) in Intel 8086 and x86 Processors

Interrupt Priority

The table shows interrupt priority in 8086. $$ \begin{array}{|c|c|} \hline \text{Interrupt} & \text{Priority} \\ \hline \text{Divide error, INT n, INTO} & \text{Highest}\\ \text{NMI} & \downarrow \\ \text{INTR} & \downarrow \\ \text{Single Step} & {Lowest} \\ \hline \end{array} $$

Servicing Interrupt by 8086

Intel 8086 performs following operations for servicing the Interrupt:

1. The SP is decremented by two and the content of flag register is pushed to stack memory.
2. The interrupt system is disabled by clearing Interrupt Flag(IF).
3. The single-step trap flag is disabled by clearing Trap Flag(TF).
4. The stack pointer is decremented by two and the content of CS register is pushed to stack memory.
5. Again, the stack pointer is decremented by two and the content of IP is pushed to stack memory.
6. In case of hardware interrupt through INTR, the processor runs an interrupt acknowledge cycle to get the interrupt type number. For software interrupts, the type number is specified in the instruction itself. For NMI and exceptions the type number is defined by INTEL.
7. The processor generates a 20-bit memory address by multiplying the type number by four and sign extending it to 20-bit. This memory address is the address of the interrupt vector table, where the vector address of the Interrupt Service Subroutine (ISS) is stored by the user/system designer.
8. The first word pointed by vector table address is loaded in IP and the next word is loaded in CS register. Now the content of the IP is the offset address and the content of the CS.register is the segment base address of the ISS to be executed.
9. The 20-bit physical memory address of ISS is calculated by multiplying the content of CS register by 16₁₀ and adding it to the content of IP.
10. The processor executes the ISS to service the interrupt.
11. The ISS will be terminated by the IRET instruction. When this instruction is executed, the top of stack is poped to IP, CS and flag register one word by one word. After every pop operation, the SP is incremented by two.
12. Thus, at the end of ISS, the previous status of the processor is restored and so the processor will resume the execution of normal program from the instruction where it was suspended.